1. Field of the Invention
The present invention relates to integrated circuits and their operation.
2. Description of Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. LABs (comprising multiple LEs) may be connected to horizontal and vertical lines that may or may not extend the length of the PLD.
Logic elements, including LUT-based logic elements, typically include configurable elements holding configuration data that determine the particular function or functions carried out by the logic element. A typical LUT circuit may include RAM bits that hold data (a “1” or “0”). However, other types of configurable elements may be used. Some examples may include static, magnetic, ferro-electric or dynamic random access memory, electrically erasable read-only memory, flash, fuse, and anti-fuse programmable connections. The programming of configuration elements could also be implemented through mask programming during fabrication of the device. While mask programming may have disadvantages relative to some of the field programmable options already listed, it may be useful in certain high volume applications. For purposes herein, the generic term “memory element” will be used to refer to any programmable element that may be configured to determine functions implemented by a PLD.
As discussed above, PLDs are commonly constructed using a lookup table (LUT) as the basic logic element. For example, a K-input lookup table (K-LUT) typically includes 2K programmable memory elements, and a 2K to 1 multiplexer, selecting one of the storage elements under the control of the K select inputs to the multiplexer. These K inputs can be considered to be the inputs to a K-input logic function which can implement any particular required logic function by setting the contents of the memory elements to the appropriate values.
There is a tradeoff between cost and speed of a logic circuit constructed with LUTs. Typically the cost of each LUT grows exponentially with the choice of K, but the number of LUTs required to build a logic circuit decreases more slowly with larger values of K. However, the number of LUTs that are in series for a larger value of K will be reduced, making the logic circuit faster. Some designs use fracturable LUTs that can be configured as one or more LUTs with different numbers of inputs, for example as either a single 6-LUT or two 4-LUTs. U.S. Pat. No. 7,312,632 provides examples of such fracturable LUTs.